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Chip technology

Samsung sharpens DRAM marketing prowess vs Micron

May 05, 2021 (Gmt+09:00)

Samsung Electronics' Jay Y. Lee (third from right) views EUV equipment at ASML plant in the Netherlands in 2020.
Samsung Electronics' Jay Y. Lee (third from right) views EUV equipment at ASML plant in the Netherlands in 2020.


During Samsung Electronics Co.'s first-quarter conference call with analysts on Apr. 26, UBS analyst Nicolas Gaudois asked about the South Korean chipmaker's mass production schedule for its third-generation or "1z" DRAM chips.

"1z DRAM refers to the 15-nanometer (nm) node," Samsung's Senior Vice President for the memory business Han Jinman said in reply to the question.

His answer, unexpectedly specific, surprised the conference call participants. It was the first time since February 2015 that the world's largest memory chipmaker gave the exact number in public about its next DRAM technology node, or the line width of a circuit through which electricity flows.

His remarks were initially regarded as a mistake. But it was later confirmed that he leaked the number intentionally, which analysts said were aimed at showing the tech heavyweight's confidence in its chip technology, in particular, over third-ranked Micron Technology Inc.

In January this year, Micron announced that it had developed the world’s most advanced DRAM process technology, called “1α” (1-alpha). At the time, the US chipmaker said the new process could be taken as the fourth generation of the 10nm class, for which it switched to the Greek alphabet, breaking away from the industry's naming conventions using letters from the roman alphabet: x, y and z.

The announcement caught Samsung off guard, spawning market speculation that the sector leader no longer maintained its technology gap with Micron. 

In response, Samsung Electronics has decided to precisely reveal the line width of its DRAM chips and to step up marketing competition for its sophisticated DRAM technology, according to semiconductor industry sources on May 5.

The line width is a key yardstick of chipmakers' technological prowess. By reducing the line width, the DRAM can achieve higher energy efficiency and faster processing speeds.

Samsung Electronics Vice President Jay Y. Lee inspects a Pyeongtaek chip plant that adopted extreme ultraviolet lithography technology in January 2021 
Samsung Electronics Vice President Jay Y. Lee inspects a Pyeongtaek chip plant that adopted extreme ultraviolet lithography technology in January 2021 
It had been customary not to reveal the exact line width of DRAMs over the past five to six years. Since Samsung produced the world's first DRAM in the 10 nm range in 2016, chipmakers have refrained from aggressive marketing and technology competition. It takes two to three years to reduce the line width of a circuit by 1 nm.

The first-generation DRAM in the 10 nm process node was termed "1x," followed by "1y" for its second generation and "1z" for its third generation. 

Market observers had estimated the "1x" DRAM had a line width at the higher end of the 10 nm range, with the "1z" at the mid-10 nm range. Accordingly, it had been difficult to exactly compare the specifications between Samsung's 1z DRAM and SK Hynix Inc.'s 1z DRAM.

An industry source said Samsung's disclosure of the exact number about its third-generation "1z" DRAM seemed aimed at reducing market confusion in the increasingly competitive DRAM market, ahead of the mass production of the thinner, "14 nm DRAM" in the second half of this year.

Samsung has claimed the top spot in the DRAM market since it mass produced the world's first DRAM in the 10 nm process in 2016. It had maintained its technological gap by a half or one year over second- and third-ranked SK Hynix Inc. and Micron Technology.

It was also the world's first chipmaker to unveil the third-generation "1z" DRAM in 2019. Under such circumstances, it felt no need to disclose how specifically it has shrunk the DRAM circuit. 

But the atmosphere has changed since Micron claimed the world's first development and production of the fourth-generation "1α" DRAM last January.

The race for thinner DRAM chips has been intensifying as chipmakers began to use the extreme ultraviolet (EUV) scanner, which had been used for the 7 nm process or thinner, for thicker DRAMs. A EUV scanner uses lithography technology to draw elaborate and detailed patterns on semiconductor wafers.

Taiwan-based memory chipmaker Nanya Technology, the world's fourth-largest DRAM chipmaker, plans to utilize EUV lithography technology for the 10 nm process to narrow its gap with the market leaders. 

Samsung sharpens DRAM marketing prowess vs Micron

Some remain doubtful about whether Micron's "1α" DRAM could be recognized as the fourth-generation DRAM. The US chipmaker has not yet shown the pictures of the new chip. 

"DRAMs, even in the same category, show clear differences in technology," said a college professor of the semiconductor department. "That Samsung, at the forefront of technology, gave the number of its latest DRAM is kind of declaration that it does not want to be treated the same."  

Other DRAM manufacturers, however, expressed concerns about escalating technology marketing competition.

"It's hard to understand why Samsung did so all of a sudden," said a DRAM industry source, referring to the latter's disclosure of the detailed DRAM node.

By Jeong-Su Hwang

hjs@hankyung.com

Yeonhee Kim edited this article.

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